불휘발성 반도체기억장치

Nonvolatile semiconductor memory

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A nonvolatile semiconductor memory device according to the present invention comprises a memory cell array (311) composed of a collection of blocks (313-1, 313-2, ..., 313-n), each block containing memory cells sharing the source or drain, a first region (302) having the memory cell array formed in its surface region, and a control circuit (312) that, in the erase mode, sets the source shared by a plurality of memory cells to be erased in one block at a first potential (VS1, ..., VSn, VS1', ..., VSn') and the first region at a second potential (VW) higher than the GND potential and lower than the first potential, and at the same time, sets the source shared by a plurality of memory cells not to be erased in other blocks at a third potential (VG11, ..., VGn, VG1', ..., VGn') equal to or higher than the second potential and lower than the first potential. <IMAGE>

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